Sr. Analog Layout Design Engineer

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THE ROLE:

The full custom IC layout group is looking for a candidate to design the layout for digital and analog circuits based on schematics using industry­ leading CAD tools and cutting ­edge foundry technology. Examples of layout designed by our team include Phase­ Locked Loop (PLL), Delay ­Locked Loop (DLL), Voltage Controlled Oscillator (VCO), Digital to Analog Converter (DAC), Current Regulator, High Speed Differential Signaling circuitry, Droop Detect, and Die Crack Monitor. Proficiency in 2D layout design while being able to visualize in 3D space are traits ideal for this position. It is useful to have knowledge of digital and analog circuitry at the CMOS transistor level.

The candidate will be able to see through the different stages of a project development – from initial floor planning and routing of low level logic gates through top level integration of numerous blocks and ultimately, project tape out related tasks. Day to day responsibilities include layout of lower level cells, assembly of these lower level cells into macros/pads and assembly of these macros/pads into an I/O ring database. You will be running various verification tools at all levels of the design hierarchy. These include DRC, LVS, EM/IR, ERC and Latch up/ESD. Prior experience training and leading junior resources preferred. This team is essential to the success of AMD as a cutting­ edge company. You will be working on some of the most exciting projects the industry has to offer. It is a very exciting environment and you will be working with the very best in our technology.

THE PERSON:

• Strong communication, leadership analytical thinking and problem-solving skills, excellent attention to detail
• Possesses good teamwork, communication and interpersonal skills
• A self-starter and able to independently drive tasks to completion
• Enjoys working in a fast-paced, multi-project team environment using state of the art tools and technology
• Possesses a continuous improvement mind-set

KEY RESPONSIBILITIES:

• Layout of basic digital and analog building blocks using analog transistor level components
• Layout of analog macros, power pads, and input/output pads using above blocks
• Creation of black­box models for other groups in the design flow
• Verification of layout using Cadence and Calibre tools
• Overseeing contractors on layout

PREFERRED EXPEREINCE:

• Must have detailed knowledge of CMOS circuit theory. Ideal candidate will have experience in the 5nm/3nm space.
• Must have ability to communicate with various teams to articulate specs and requirements as they pertain to layout
• Layout design and verification experience using Cadence Virtuoso and Mentor Calibre tools
• Strong experience in layout design.
• Knowledge of chip level integration and ESD concepts a plus
• Perl programming, TCL and SKILL programming not required, but would be advantages

ACADEMIC CREDENTIALS: Electrical/Computer Engineering Degree and/or Electronics related Diploma

LOCATION: Markham, Vancouver, Ottawa

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